1. Field of the Invention
The present invention relates to semiconductor devices, and in particular to methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/xcexcm or below) and a channel length (sub-lithographic, e.g., 0.1 xcexcm or less) that is shorter than the lithography-defined gate lengths.
2. Background of the Invention
As MOSFET channel lengths are scaled down to sub-0.1 xcexcm dimensions and as the-gate oxide thickness is scaled down to below 1.5 nm, tunneling currents larger than 1 A/cm2 will preclude the use of SiO2 as a gate dielectric layer. Therefore, the development of a Complementary Metal Oxide Semiconductor (CMOS) technology which utilizes a high-k gate insulator is a must for the continuing of CMOS scaling into the sub-0.1 xcexcm regime.
In conventional gate CMOS technologies wherein high-k gate insulators are employed, the activation anneal of the source/drain implants is typically performed after the gate insulator is formed. This limits the anneal temperature to less than 800xc2x0 C. to prevent degradation of the properties of the high-k insulator. Such low temperature anneals result in partial activation of the source/drain junctions as well as in depletion of the polysilicon gate. Both of the above mentioned characteristics are undesirable since they oftentimes lead to device performance degradation.
Moreover, in conventional gate CMOS technologies, the source/drain extensions must overlap the gate region of the device. This overlap causes capacitance in the device. The greater the overlap of the source/drain extensions with the gate region, the greater the overlap capacitance is. Likewise, if the overlap of the source/drain extensions with the gate is too small, an unreliable MOSFET device may be fabricated.
Another problem associated with conventional gate-CMOS technologies is that the gate is fabricated utilizing lithography and etching. The use of lithography and etching in forming the gate region of the CMOS device provides a MOSFET device whose channel length is in the same order as the lithographic tool. That is, lithography-defined gate length preclude the formation of sub-lithographic devices.
In view of the drawbacks with prior art gate CMOS technologies, there is a continued need to develop new and-improved methods that will permit the fabrication of MOSFET devices that have a high-k gate insulator, low overlap capacitance and a sub-lithographic channel length.
One object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that contains a high-k dielectric material as the gate insulator of the device.
A further object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that contains a high-k dielectric gate insulator and a low overlap capacitance.
Another object of the present invention is to provide a method of fabricating a highly reliable MOSFET device that has a high-k gate insulator, low overlap capacitance and a short channel length.
A still further object of the present invention is to provide methods of fabricating a highly reliable MOSFET device having low overlap capacitance and a short channel length in which a high-k, low-temperature metal oxide or a high-k, high-temperature metal oxide is employed as the gate insulator of the device.
The term xe2x80x9chigh kxe2x80x9d is used in the present invention to denote a dielectric material that has a dielectric constant greater than Si3N4, i.e., greater than 7.0. More preferably, the term xe2x80x9chigh kxe2x80x9d denotes a dielectric material having a dielectric constant of 15 or above.
The term xe2x80x9clow overlap capacitancexe2x80x9d is used in the present invention to denote a capacitance of 0.35 fF/xcexcm or less.
The term xe2x80x9cshort channel lengthxe2x80x9d is employed in the present invention to denote a gate channel that lies beneath the gate region whose length is 0.1 xcexcm or less, i.e., sub-lithographic.
The term xe2x80x9chigh-temperature metal oxidexe2x80x9d denotes a metal oxide that does not degrade when subjected to annealing at a temperature of about 950xc2x0-1050xc2x0 C., preferably 1000xc2x0 C., 10 seconds. Illustrative examples of metal oxides within this class include, but are not limited to: Al2O3 and TiO2.
The term xe2x80x9clow-temperature metal oxidexe2x80x9d denotes a metal oxide that is converted to a metal or it becomes leaky upon annealing at 950xc2x0-1050xc2x0 C., preferably 1000xc2x0 C., 10 seconds. Illustrative examples of metal oxides within this class include, but are not limited to: ZrO2, barium titanate, strontium titanate and barium strontium titanate.
These and other objects and advantages can be achieved in the present invention by utilizing a method which includes a damascene processing step for the formation of the gate electrode and a chemical oxide removal (COR) processing step for producing a large taper in the pad oxide layer. When these two processing steps are used in combination with a high-k dielectric material, a MOSFET device having a low overlap capacitance and a short channel length can be fabricated.
In one embodiment of the present invention wherein a high-k, high-temperature metal oxide is employed as the gate insulator, the processing steps of the present invention comprise:
(a) providing a semiconductor structure having a film stack formed on a surface of a substrate, said film stack comprising at least a pad oxide layer formed on said surface of said substrate and a nitride layer formed on said pad oxide layer;
(b) forming a gate hole in said nitride layer stopping on said pad oxide layer;
(c) forming an oxide film on the nitride layer in said gate hole;
(d) etching said oxide film and a portion of said pad oxide layer so as to provide an opening in said gate hole exposing a portion of said substrate, wherein the pad oxide layer is tapered by said etching;
(e) forming a high-k, high-temperature metal oxide layer about said gate hole and on said exposed substrate;
(f) filling said gate hole with a gate conductor;
(g) removing said nitride layer exposing portions of said high-k, high-temperature metal oxide; and
(h) completing fabrication of said MOSFET device.
Step (h) includes forming activated source/drain extensions in said substrate beneath said gate conductor; forming spacers on exposed sidewalls of said high-k, high-temperature metal oxide; forming activated source/drain regions in said substrate; and forming silicide regions in portions of said pad oxide layer and in said gate conductor.
In another embodiment of the present invention, wherein a high-k, low-temperature metal oxide is employed as the gate insulator, the processing steps of the present invention comprise:
(i) providing a semiconductor structure having a dummy film stack formed on a surface of a substrate, said dummy film stack comprising at least a pad oxide layer formed on said surface of said substrate, a polysilicon layer formed on said pad oxide layer, and a SiO2 layer formed on said polysilicon layer;
(ii) removing selective portions of said dummy film stack stopping on said pad oxide layer so as to provide a patterned dummy gate region;
(iii) removing said SiO2 layer from said patterned dummy gate region;
(iv) forming activated source/drain extensions in said substrate beneath said dummy gate region;
(v) forming spacers on sidewalls of said dummy gate region;
(vi) forming activated source/drain regions in said substrate;
(vii) forming silicide regions in portions of said pad oxide layer and in said polysilicon layer of said dummy gate region;
(viii) forming an insulator layer surrounding said dummy gate region;
(ix) planarizing said insulator layer stopping at said polysilicon layer in said dummy gate region;
(x) forming an opening so as to expose a portion of said substrate, said opening being formed by removing said polysilicon layer of said dummy gate and by tapering a portion of said pad oxide layer of said dummy gate region;
(xi) forming a high-k, low-temperature metal oxide in said opening; and
(xii) filling said opening with a gate conductor, said gate conductor being formed at a low temperature.
An optional planarization process may follow step (xii).
Another aspect of the present invention relates to MOSFET devices that are fabricated utilizing either of the above methods. The MOSFET devices of the present invention are characterized as having a low overlap capacitance and a short channel length. Specifically, the MOSFET devices of the present invention comprise at least a gate region having a high-k gate insulator formed on at least a portion of a tapered pad oxide layer, wherein said gate region further includes a channel whose length is sub-lithographic, preferably 0.1 xcexcm or less.